1. Field of the Invention
The present invention relates to a refresh control method of a semiconductor memory device, and particularly to a reduction in current consumption in a standby state.
2. Description of the Related Art
A semiconductor memory device requiring a refresh operation must perform a refresh operation on a regular basis even in a standby state in which a low current consumption operation is required. A reduction in current consumption at the refresh operation is essential.
In memory cells installed in a semiconductor memory device in general, each of characteristics for holding data stored therein has some width. Therefore, a refresh cycle tREF equivalent to a time interval in which the same memory cells are refreshed, must be set to a value worst in data-holding characteristics. However, it is enough for memory cells each having more excellent data-holding characteristics if the refresh operation is performed in a cycle longer than the set refresh cycle tREF. Therefore, there has been proposed a so-called refresh-thinning-out operation in which one refresh operation is effected on each of memory cells each having satisfactory data-holding characteristics every 2 cycles or more of the refresh cycle tREF. Thus, the number of refresh operations per predetermined time can be reduced and current consumption at the refresh operation can be reduced.
A semiconductor memory device having a refresh-thinning-out function has been disclosed in Japanese Laid-Open Patent publication No. 9-102193. FIG. 24 mainly shows a circuit configuration of a row address system. The same figure shows, as an example, a case in which a /CAS before/RAS (hereinafter abbreviated as “CBR”) refresh operation is provided with a refresh-thinning-out function.
A timing circuit 131 outputs a trigger signal corresponding to an activation signal φR for activating a row address decoder 137 with predetermined timing according to a control signal supplied to a control terminal 101. This trigger signal is inputted to an AND logic gate 400b. Further, the timing circuit 131 outputs an activation signal φ1 for activating a refresh-thinning-out control circuit 105 to be described later.
A row address buffer 132 latches an address signal supplied to address terminal 101 at a fall time of a control signal /RAS and supplies the latched address signal to an address selector 135 as row address Add(O).
A CBR judgment circuit 133 outputs a refresh command signal φCBR according to the execution of the setting of a CBR refresh mode.
A CBR counter 134 counts the falling edge of the refresh command signal φCBR and outputs refresh address Add(C) to an address selector 135.
The address selector 135 is controlled by the refresh command signal φCBR to couple or link the row address buffer 132 and the row address decoder 137 upon read and write operations and couple the CBR counter 134 and the row address decoder 137 upon the refresh operation.
The refresh-thinning-out control circuit 105 activated by the activation signal φ1 is inputted with the refresh address Add(C) outputted from the CBR counter 134 and judges whether the address Add (C) is a registered address. The refresh-thinning-out control circuit 105 outputs a refresh permission signal φ2 to the other input terminal of the AND logic gate 400b according to the result of judgment to control the output of the activation signal φR.
The row address decoder 137 is activated by the activation signal φR to thereby allow a word driver 104 to activate any one of a plurality of word lines (WL0 through WLn) in a memory-cell array 140 according to the row address Add(O) or refresh address Add(C) inputted via the address selector 135.
Namely, since a control signal /RAS falls ahead of a control signal /CAS in a normal write/read cycle, an output signal φCBR of the CBR judgment circuit 133 is held at a deactivation level. Therefore, the address selector 135 outputs row address Add(O) outputted from the row address buffer 132 to the row address decoder 137. Thereafter, the row address decoder 137 is activated by an activation signal φR produced by the timing circuit 131 to thereby activate the corresponding word line corresponding to the write/read cycle.
Since the control signal /CAS falls ahead of the control signal /RAS in a CBR refresh cycle, the output signal φCBR of the CBR judgment circuit 133 is brought to an activation level. Therefore, the address selector 135 outputs refresh address Add(C) outputted from the CBR counter 134 to the row address decoder 137. When the refresh address Add(C) and its corresponding registered address coincide with each other at this time, a permission signal φ2 is activated and an activation signal φR is supplied to the row address decoder 137, so that a word line corresponding to the refresh address Add(C) is activated. When they are found not to coincide with each other, the activation signal φR is masked so that no word line is activated.
FIG. 25 shows a circuit diagram of the refresh-thinning-out control circuit 105 with being taken as the center. n+1 bit internal address signals A0′-An′ and their inverted signals /A0′-/An′, which constitute refresh address Add(C) outputted from a CBR counter 134, are inputted to address registration circuits 1.1-1.r. 
The address registration circuits 1.1-1.r are respectively provided with an NMOS transistor 600, and fuses 7.0-7.n and NMOS transistors 8.0-8.n, and fuses 7.0′-7.n′ and NMOS transistors 8.0′-8.n′ respectively provided in association with the address signals A0′-An′ and their inverted signals /A0′-/An′.
When the refresh address Add(C) coincides with any of addresses registered in the address registration circuits 1.1-1.r, a signal corresponding to any of outputs φH1-φHr of the address registration circuits 1.1-1.r is brought to a high level, and hence a refresh permission signal φ2 is rendered high in level.
As a result of an increase in the function required for a portable device with the popularization thereof, there has recently been a further demand for a large-capacity memory as an alternative to the conventionally-mounted static random access memory (hereinafter called “SRAM”). Since it is necessary to package or mount the memory in a limited space at the actual price, a refresh-function built-in DRAM so called pseudo SRRAM, having built in control related to a refresh operation peculiar to a memory cell such as a DRAM has been used while each memory cell for a dynamic random access memory (hereinafter called “DRAM”) formed in high integration and low in bit unit price is being used as an alternative to each memory cell of the SRAM. Thus, an external controller controls the operation for performing a self-refresh command or for conducting self-refresh operation during an external access-free period then, pseudo SRAM has been equipped with a so-called self-refresh mode in which control or the like on each refresh address is preformed. In reply to a future's high-speed demand, specs of a so-called pseudo SSRAM adapted to external specs of a synchronous SRAM (hereinafter called “SSRAM”) are becoming a reality.
However, the semiconductor memory device having the refresh-thinning-out function, which has been illustrated in Japanese Laid-open Patent Publication No. 9-102193, needs to register row addresses requiring the execution of refresh every refresh cycle tREF through the use of the address registration circuits 1.1-1.r and requires the address registration circuits 1.1-1.r every row address. Further, the respective address registration circuits 1.1-1.r respectively need fuses corresponding to bit widths of the row address. Namely, the total number of fuses to be mounted to the semiconductor memory device needs (bit widths of row address)×(number of row addresses to perform refresh every cycle). In order to obtain an effective reduction effect of current consumption by the refresh operation with respect to the distribution of data-holding characteristics in the semiconductor memory device, a large number of fuses must be provided and an increase in die size of the semiconductor memory device might be incurred, thus resulting in a problem.
Since a large number of fuses are cut when the corresponding addresses are registered in the address registration circuits 1.1-1.r, much test time is needed. It is further assumed that since the refresh address Add(C) is generated by the built-in counter, external control is restricted, and much test time is required upon execution of a functional test even in the case of, for example, the setting of refresh-thinning-out control on each redundant region for substituting a characteristic defective cell with another, thus causing a problem.
Since the refresh address Add(C) is connected even to the refresh-thinning-out control circuit 105 as well as to the row address buffer 137, the CBR counter 134 must drive these loads, thus being in danger of causing an increase in drive current. Since the refresh-thinning-out control circuit 105 takes such a configuration as to always make a comparison between the refresh address Add(C) and each registered address regardless of judgment as to execution/non-execution of the refresh operation, unnecessary currents consumed will flow even during a judgment operation-free period. A problem arises in that this is danger of being unable to meet the demand for low current consumption due to these currents consumed. Since the current consumption is originally low upon standby in particular, the rate of an operating current of the refresh-thinning-out control circuit 105 to the total current consumption becomes large, thus resulting in a problem for the reduction in current consumption.
While the load on the external controller for the refresh operation has heretofore been significantly lightened in the semiconductor memory device called the pseudo SRAM or pseudo SSRAM, there is still a need to perform its control by the external controller. There may be a case in which it is necessary to provide a dedicated control terminal upon its control. Therefore, it is hard to say that the conventional pseudo SRAM or the like has the perfect compatibility with an SRAM or SSRAM in which such control or a dedicated control terminal is unnecessary. To this end, there has been proposed a semiconductor memory device having such specs that in order to bring the compatibility near to the perfect one, a refresh operation and a normal read/write operation are executed independently of each other with occasional timing while the refresh operation is being incorporated therein as an internal access operation. However, the semiconductor memory device is accompanied by a problem that when a refresh-thinning-out function is added thereto, a refresh operating time might be long due to the time required to make a decision as to refresh address by a refresh-thinning-out control, and a delay in propagation due to a load imposed on the refresh address on a signal path, thus causing a possibility that an operational cycle time will become long.